CMOS high impedance circuit

ABSTRACT

A high impedance circuit includes a diode-connected MOSFET circuit. This circuit may be used in a buffer amplifier of a hearing aid microphone, coupled across an input of the buffer amplifier and providing a high input impedance.

BACKGROUND OF THE INVENTION

[0001] This specification describes, with reference to the accompanyingdrawings, a novel and improved high impedance circuit. While thiscircuit may be used in any application requiring a high impedance, lownoise circuit, the description below refers specifically to its use asan input bias circuit for a preamplifier circuit for a microphonecomponent of a hearing aid.

[0002] Generally speaking, a hearing aid utilizes three basiccomponents, a microphone, an amplifier and a receiver or loudspeakercomponent. Briefly, the microphone generally includes a transducer forconverting incoming sound pressure levels to corresponding electricalsignals. The amplifier amplifies these electrical signals to a desiredlevel, and the receiver or loudspeaker component translates theseamplified electrical signals to an acoustical sound output, or outgoingsound pressure level.

[0003] Generally, the microphone component includes a transducer such asan electret microphone, and a buffer amplifier or “preamplifier.” Often,a CMOS amplifier component is used as the preamplifier. The input ofthis CMOS preamplifier must be biased to ground level. However, sincethe signal source in the electret microphone is typically a relativelysmall capacitor, the impedance of the preamplifier input should berelatively large, and preferably, as large as possible. Currently, biasresistor values of about 10 Gohms are utilized. For further noisereduction, this value might be increased up to 100 Gohms. However, theseresistors cannot be implemented on ICs but must be made on a thick filmhybrid. As an alternative to the resistors for the preamplifier inputimpedance, a pair of small diodes coupled in parallel but in oppositepolarity (i.e., “antiparallel”) are sometimes used. This permits arelatively large impedance value to be obtained, which value is stronglydependant upon process variations. However, the use of diodes for thispurpose has the disadvantages of slow settling and slow overloadrecovery, which are characteristics of diodes.

[0004] In devices presently on the market, the bias voltage for theinput of a preamplifier is supplied through a high-ohmic resistance orthrough a pair of anti-parallel diodes. In order to preserve thesignal-to-noise ratio, the impedance of such device must be very high.On the other hand, the impedance has a certain maximum level, in orderto enable a fast startup of the amplifier, and a fast recovery afteroverload. An integrated diode pair forms too high an impedance forguaranteeing stability; however, adding a parallel resistor (10-100Gohms) introduces a level of noise.

OBJECTS AND SUMMARY OF THE INVENTION

[0005] Accordingly, it is an object of the invention to provide a highimpedance circuit which overcomes the above-noted shortcomings ofutilizing bias resistors or reverse-polarized parallel diodes.

[0006] In accordance with the foregoing, a high impedance input circuitfor a buffer amplifier/preamplifier of a hearing aid microphonecomprises a CMOS transistor circuit coupled across an input of saidbuffer amplifier/preamplifier and providing a high impedance.

[0007] In accordance with another aspect of the invention, a highimpedance input circuit for a buffer amplifier/preamplifier of a hearingaid microphone comprises a diode-connected MOSFET circuit.

[0008] In accordance another aspect of the invention, a high impedancecircuit comprises a CMOS transistor circuit providing a high impedanceequivalent to a pair of antiparallel diodes.

[0009] In accordance with another aspect of the invention, a highimpedance circuit comprises a diode-connected MOSFET circuit.

[0010] In accordance with another aspect of the invention, a method ofconstructing a high impedance circuit comprises forming on an integratedchip at least one p-channel transistor and at least one n-channeltransistor coupled in circuit to provide a diode-switched highimpedance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the accompanying drawings:

[0012]FIG. 1 is a schematic circuit diagram of a prior art microphonecircuit for a hearing aid;

[0013]FIG. 2 is a schematic circuit diagram of an alternate form ofprior art microphone circuit;

[0014]FIG. 3 is a schematic circuit diagram of a high input impedancedevice for a hearing aid microphone in accordance with the presentinvention;

[0015]FIG. 4 is a graph showing the impedance of an n-channel device;

[0016]FIG. 5 is a graph showing the impedance of an p-channel device;and

[0017]FIG. 6 is a graph showing the impedance of two n-channel devicesin parallel;

[0018]FIG. 7 is a graph showing the impedance of two p-channel devicesin parallel; and

[0019]FIG. 8 is a graph showing the impedance of the circuit of FIG. 3.

DETAILED DESCRIPTION OF THE DRAWINGS

[0020] The Prior Art

[0021] Referring initially to FIG. 1, a schematic circuit diagram of amicrophone 10 for a hearing aid is designated generally by the referencenumeral 10. The microphone includes a transducer component 12 such as anelectret microphone which is symbolized in FIG. 1 as a current source.The microphone 10 also includes a buffer amplifier/preamplifier circuitportion 14 (hereinafter “preamplifier”) which may comprise an MOS fieldeffect transistor (FET) 16 wired in a common source configuration. Apositive voltage 18 is provided with a suitable biasing resistor 19 forthe transistor 16. A common or negative voltage connection 20 is alsoprovided. The source electrode of the FET 16 provides the output 22 ofthe preamplifier 14. The preamplifier circuit 14 may be realized on asingle integrated circuit (IC) chip 15.

[0022] The input of the preamplifier 14 for the microphone 10 must bebiased to ground level. Since the signal source in the electret 12 is avery small capacitor, the impedance of the amplifier input must be aslarge as possible. Currently, a bias resistor 24 of about 10 Gohms isused. For reasons of noise reduction this value may be increased up to100 Gohms. These resistors cannot be realized on IC's, therefore theyare usually made on a thick film hybrid.

[0023] Referring to FIG. 2, a similar microphone 10 employing anelectret transducer or microphone 12 and a preamplifier circuit 14, onan IC chip 15, is illustrated. Like reference numerals are utilized todesignate like elements in FIG. 2.

[0024] In FIG. 2, the input impedance for the preamplifier 14 may beintegrated onto the same chip 15 in the form of a pair of paralleldiodes 26, 28 connected in reverse polarity. As indicated above, arelatively large impedance value can be obtained by the use of suchdiodes 26, 28, however, the value is strongly dependant on processvariations. That is, it is difficult in the integrated circuitmanufacture process to accurately predict the value of the impedanceobtained by use of diodes 26, 28 within acceptable tolerance levels. Thediodes 26, 28 also exhibit properties typical of diodes, in that theyare relatively slow in settling of the voltage over the diode orreaching steady state conditions, exhibit relatively slow overloadrecovery times, and the like.

[0025] The Invention

[0026] Referring to FIG. 3, like reference numerals are again utilizedto designate like elements and components. In accordance with theinvention, the input impedance in FIG. 3 is provided by an additionalCMOS transistor or MOSFET circuit 30.

[0027] The MOSFET circuit 30 is used as a high impedancetransconductance. The MOS transistor circuit 30 may be integrated byCMOS technology onto the same chip 15 as the preamplifier circuit 14.Alternatively, the components of circuit 30 may be integrated on thesame chip with the existing components of FIG. 2, with the circuit 30 inparallel with the diodes 26, 28. This approach affords some economy inthat the entire chip does not have to be redesigned and refabricated.The specifications of the MOSFET circuit 30 are such that the influenceof the diodes 26, 28 on its performance is negligible. Of course, thechip may be fabricated without the diodes 26, 28, if desired.

[0028] The MOSFET circuit 30 is designed so that the impedance is alwayshigher than some selected minimum value, e.g. 50-100 Gohms, at theminimum control voltage.

[0029] In FIG. 3 “diode-connected” MOSFETs 90, 92, 94, 96 are used. Bothp-channel 90, 92 and n-channel 94, 96 devices are used in theconfiguration shown in order to obtain symmetry. The circuit of fourMOSFETS may be parallel with a diode pair 26, 28 of FIG. 2, as notedabove.

[0030] The graph of FIG. 4 shows the impedance curve of two ways toconnect an n-channel device. The curve marked 100 is the impedance ofthe n-channel device 96 of FIG. 3, and the curve marked 102 is theimpedance of the n-channel device 94 of FIG. 3. The bulk connections areall grounded. The impedance of the parallel connection of bothn-channels devices (FIG. 6) is almost symmetrical for positive andnegative input voltages.

[0031] The graph of FIG. 5 shows the impedance curves of two ways toconnect a p-channel device. The curve marked 104 is the impedance of thep-channel device 92 of FIG. 3, and the curve marked 106 is the impedanceof the p-channel device 90 of FIG. 3. The impedance of the parallelconnection of both p-channels devices (FIG. 7) is almost symmetrical forpositive and negative input voltages, and is a mirror image comparedwith the n-channels graph of FIG. 6.

[0032] The graphs for the p-channel devices (FIGS. 5 and 7) show thesame behavior, and are mirror images compared with the n-channels graphsof FIGS. 4 and 6.

[0033] The graph of FIG. 8 shows the impedance of the series connectionof the n-channel pair and the p-channel pair of FIG. 3. This graph issymmetrical. The devices are scaled, so that the impedance at zero biasvoltage is at the desired level. At this point, all devices contributeto the total impedance equally, so that the sensitivity of the impedancedue to component variation is minimal.

[0034] The above-described high impedance bias circuit of the invention,as illustrated and described above with reference to FIGS. 3-8 offers anumber of advantages over the prior art shown and described withreference to FIGS. 1 and 2. Among other things, the circuitry of theinvention can be integrated onto a common chip with the bufferamplifier/preamplifier circuitry. Unlike the diodes utilized in theembodiment of FIG. 2, the circuit of the invention is relativelyinsensitive to process variations in the IC manufacture process. Theextremely high impedance which can be achieved by the circuitry of theinvention minimizes the noise figure and optimizes signal to noise ratioof the microphone component including the electret 12 and preamplifier14. Also, the controlled impedance of the invention further limits andminimizes input settling time of the buffer amplifier circuitry 14.

[0035] In one embodiment, the design is dimensioned, depending on thecharacteristics of the CMOS process, in such a way that the minimumimpedance (i.e., with the minimum occurring threshold voltages) of thecircuit is about 100 Gohms. The maximum impedance is about a factor of10 higher.

[0036] Among the advantages of the above-described invention are: Theimpedance is more stable for process variations than the impedance ofthe anti-parallel diodes.

[0037] The circuit is much simpler and requires much less chip area thanthe advanced “high impedance bias device.”

[0038] The additional parasitic capacitance is very small (since thesizes of the MOSFETs are very small, and only small diffusion areas areconnected to the signal input).

[0039] The circuit can also be placed in parallel with the anti-paralleldiodes (in order to cover a wider range of process variations).

[0040] The circuit is passive, no risk for oscillation and nobattery/current consumption.

[0041] Linearity is very good for signals up to 300 mV amplitude.

[0042] While the CMOS high impedance circuit has been described abovewith reference to its use as a high input impedance bias circuit for aCMOS preamplifier, such as in a hearing aid, it has many other uses.

[0043] The above described CMOS high impedance circuit is a simple, verypowerful passive circuit that can be applied everywhere there is a needfor a high impedance, low noise circuit.

[0044] Examples of other applications include:

[0045] 1. As a bias device in other stages of an amplifier, e.g., aftera coupling capacitor.

[0046] 2. As a bias device in other circuits that are connected to highimpedance capacitive sensors, like Analog-to-Digital converters.

[0047] 3. As a start-up device in, e.g., reference bias sources.

[0048] 4. As a filtering device in filters that require large timeconstants.

[0049] While the present invention has been described with reference toone or more preferred embodiments, those skilled in the art willrecognize that many changes may be made thereto without departing fromthe spirit and scope of the present invention which is set forth in thefollowing claims.

What is claimed is:
 1. A high input impedance input circuit for a bufferamplifier/preamplifier of a hearing aid microphone said high inputimpedance circuit comprising: a CMOS transistor circuit providing animpedance equivalent to a pair of antiparallel diodes connected betweenan input of said buffer amplifier and a reference voltage.
 2. Thecircuit of claim 1 wherein said transistor circuit is integrated on asingle integrated circuit chip with said buffer amplifier/preamplifier.3. The circuit of claim 1 and wherein said high impedance circuitcomprises at least one p-channel MOSFET device or at least one n-channelMOSFET device, and wherein a drain terminal of said MOSFET device isconnected with said buffer amplifier input, and all other terminals ofsaid MOSFET device are connected with said reference voltage.
 4. Thecircuit of claim 1 wherein said high impedance circuit comprises atleast one p-channel MOSFET device or at least one n-channel MOSFETdevice, and wherein drain and gate terminals of said MOSFET device areconnected with said buffer amplifier input, and source and bulkterminals of said MOSFET device are connected with said referencevoltage.
 5. The circuit of claim 1 wherein said high impedance circuitcomprises a parallel connection of at least one first circuit and atleast one second circuit, said first circuit comprising at least onep-channel MOSFET device and at least one n-channel MOSFET device,wherein a drain terminal of said MOSFET device is connected with saidbuffer amplifier input, and all other terminals of said MOSFET deviceare connected with said reference voltage and said second circuitcomprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein drain and gate terminals of said MOSFETdevice are connected with said buffer amplifier input, and source andbulk terminals of said MOSFET device are connected with said referencevoltage.
 6. The circuit of claim 1 wherein said high impedance circuitcomprises the series connection of at least one first circuit and atleast one second circuit, said first circuit being connected betweensaid buffer amplifier input and a common node between said first circuitand said second circuit, and said second circuit being connected betweensaid common node and said reference voltage, wherein said first circuitcomprises a parallel connection of at least one third circuit and atleast one fourth circuit, said third circuit comprising at least onep-channel MOSFET device or at least one n-channel MOSFET device, whereina drain terminal of said MOSFET device is connected with said bufferamplifier input, and all other terminals of said MOSFET device areconnected with said common node, and said fourth circuit comprising atleast one p-channel MOSFET device or at least one n-channel MOSFETdevice, wherein drain and gate terminals of said MOSFET device areconnected with said buffer amplifier input, and source and bulkterminals of said MOSFET device are connected with said common node,said second circuit comprises a parallel connection of at least onefifth circuit and at least one sixth circuit, said fifth circuitcomprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein a drain terminal of said MOSFET deviceis connected with said common node, and all other terminals of saidMOSFET device are connected with said reference voltage, and said sixthcircuit comprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein drain and gate terminals of said MOSFETdevice are connected with said common node, and source and bulkterminals of said MOSFET device are connected with said referencevoltage.
 7. A method of constructing high input impedance input circuitfor a buffer amplifier/preamplifier of a hearing aid microphone on asingle integrated circuit chip with said buffer amplifier/preamplifiersaid method comprising: forming on said integrated circuit chip at leastone p-channel transistor or at least one n-channel transistor coupledacross an input of said buffer amplifier/preamplifier and providing ahigh impedance.
 8. The method of claim 7 and wherein said high impedancecomprises a symmetrical high impedance.
 9. The method of claim 8 whereinsaid forming at least one transistor comprises forming a diode-connectedMOS component.
 10. The method of claim 7 wherein said forming at leastone transistor includes forming at least one p-channel MOSFET device orat least one n-channel MOSFET device, connecting a drain terminal ofsaid MO SFET device with an input of said buffer amplifier andconnecting all other terminals of said MOSFET device with a referencevoltage.
 11. The method of claim 7 wherein said forming includes formingat least one p-channel MOSFET device or at least one n-channel MOSFETdevice, connecting drain and gate terminals of said MOSFET device withan input of said buffer amplifier and connecting source and bulkterminals of said MOSFET device with a reference voltage.
 12. The methodof claim 7 wherein said forming comprises forming at least one firstp-channel MOSFET device and at least one first n-channel MOSFET device,connecting a drain terminal of said first MOSFET device with an input ofsaid buffer amplifier and connecting all other terminals of said firstMO SFET device with a reference voltage, and forming at least one secondp-channel MOSFET device or at least one second n-channel MOSFET device,connecting drain and gate terminals of said second MOSFET device with aninput of said buffer amplifier and connecting source and bulk terminalsof said second MOSFET device with a reference voltage and connectingsaid first and second device in parallel.
 13. The method of claim 7wherein forming said circuit comprises forming the series connection ofat least one first circuit and at least one second circuit, said firstcircuit being connected between said buffer amplifier input and a commonnode between said first circuit and said second circuit, and said secondcircuit being connected between said common node and said referencevoltage, said first circuit comprises a parallel connection of at leastone third circuit and at least one fourth circuit, said third circuitcomprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein a drain terminal of said MOSFET deviceis connected with said buffer amplifier input, and all other terminalsof said MO SFET device are connected with said common node, and saidfourth circuit comprising at least one p-channel MOSFET device or atleast one n-channel MOSFET device, wherein drain and gate terminals ofsaid MOSFET device are connected with said buffer amplifier input, andsource and bulk terminals of said MOSFET device are connected with saidcommon node, said second circuit comprises a parallel connection of atleast one fifth circuit and at least one sixth circuit, said fifthcircuit comprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein a drain terminal of said MOSFET deviceis connected with said common node, and all other terminals of saidMOSFET device are connected with said reference voltage, and said sixthcircuit comprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein drain and gate terminals of said MOSFETdevice are connected with said common node, and source and bulkterminals of said MOSFET device are connected with said referencevoltage.
 14. A high input impedance input circuit for a bufferamplifier/preamplifier of a hearing aid microphone, said high inputimpedance circuit comprising a diode-connected MOSFET circuit.
 15. Thecircuit of claim 14 wherein said MOSFET circuit comprises at least onep-channel transistor or at least one n-channel transistor.
 16. Thecircuit of claim 14 wherein said MOSFET circuit comprises two or morep-channel and/or n-channel transistors coupled in parallel or in series.17. The circuit of claim 14 wherein said MOSFET circuit includes saidhigh impedance circuit comprises at least one p-channel MOSFET device orat least one n-channel MOSFET device, and wherein a drain terminal ofsaid MOSFET device is connected with said buffer amplifier input, andall other terminals of said MOSFET device are connected with saidreference voltage.
 18. The circuit of claim 14 wherein said MOSFETcircuit includes said high impedance circuit comprises at least onep-channel MOSFET device or at least one n-channel MOSFET device, andwherein drain and gate terminals of said MOSFET device are connectedwith said buffer amplifier input, and source and bulk terminals of saidMOSFET device are connected with said reference voltage.
 19. The circuitof claim 14 wherein said high impedance circuit comprises a parallelconnection of at least one first circuit and at least one secondcircuit, said first circuit comprising at least one p-channel MOSFETdevice and at least one n-channel MOSFET device, wherein a drainterminal of said MOSFET device is connected with said buffer amplifierinput, and all other terminals of said MOSFET device are connected withsaid reference voltage and said second circuit comprising at least onep-channel MOSFET device or at least one n-channel MOSFET device, whereindrain and gate terminals of said MOSFET device are connected with saidbuffer amplifier input, and source and bulk terminals of said MOSFETdevice are connected with said reference voltage.
 20. The circuit ofclaim 14 wherein said high impedance circuit comprises the seriesconnection of at least one first circuit and at least one secondcircuit, said first circuit being connected between said bufferamplifier input and a common node between said first cirucit and saidsecond circuit, and said second circuit being connected between saidcommon node and said reference voltage, wherein said first circuitcomprises a parallel connection of at least one third circuit and atleast one fourth circuit, said third circuit comprising at least onep-channel MOSFET device or at least one n-channel MOSFET device, whereina drain terminal of said MOSFET device is connected with said bufferamplifier input, and all other terminals of said MOSFET device areconnected with said common node, and said fourth circuit comprising atleast one p-channel MOSFET device or at least one n-channel MOSFETdevice, wherein drain and gate terminals of said MOSFET device areconnected with said buffer amplifier input, and source and bulkterminals of said MOSFET device are connected with said common node,said second circuit comprises a parallel connection of at least onefifth circuit and at least one sixth circuit, said fifth circuitcomprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein a drain terminal of said MOSFET deviceis connected with said common node, and all other terminals of saidMOSFET device are connected with said reference voltage, and said sixthcircuit comprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein drain and gate terminals of said MOSFETdevice are connected with said common node, and source and bulkterminals of said MOSFET device are connected with said referencevoltage.
 21. A high input impedance circuit comprising a diode connectedMOSFET circuit.
 22. The high input impedance circuit of claim 21 whereinsaid MOSFET circuit comprises a CMOS circuit providing an impedanceequivalent to a pair of antiparallel diodes.
 23. The circuit of claim 21wherein said MOSFET circuit is integrated on a single integrated circuitchip.
 24. The circuit of claim 21 wherein said MOSFET circuit comprisesat least one p-channel transistor device or at least one n-channeltransistor device.
 25. The circuit of claim 21 wherein said MOSFETcircuit includes said high impedance circuit comprises at least onep-channel MOSFET device or at least one n-channel MOSFET device, andwherein a drain terminal of said MOSFET device is connected with saidbuffer amplifier input, and all other terminals of said MOSFET deviceare connected with said reference voltage.
 26. The circuit of claim 21wherein said MOSFET circuit includes said high impedance circuitcomprises at least one p-channel MOSFET device or at least one n-channelMOSFET device, and wherein drain and gate terminals of said MOSFETdevice are connected with said buffer amplifier input, and source andbulk terminals of said MOSFET device are connected with said referencevoltage.
 27. The circuit of claim 21 wherein said high impedance circuitcomprises a parallel connection of at least one first circuit and atleast one second circuit, said first circuit comprising at least onep-channel MOSFET device and at least one n-channel MOSFET device,wherein a drain terminal of said MOSFET device is connected with saidbuffer amplifier input, and all other terminals of said MOSFET deviceare connected with said reference voltage and said second circuitcomprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein drain and gate terminals of said MOSFETdevice are connected with said buffer amplifier input, and source andbulk terminals of said MOSFET device are connected with said referencevoltage.
 28. The circuit of claim 21 wherein said high impedance circuitcomprises the series connection of at least one first circuit and atleast one second circuit, said first circuit being connected betweensaid buffer amplifier input and a common node between said first cirucitand said second circuit, and said second circuit being connected betweensaid common node and said reference voltage, wherein said first circuitcomprises a parallel connection of at least one third circuit and atleast one fourth circuit, said third circuit comprising at least onep-channel MOSFET device or at least one n-channel MOSFET device, whereina drain terminal of said MOSFET device is connected with said bufferamplifier input, and all other terminals of said MOSFET device areconnected with said common node, and said fourth circuit comprising atleast one p-channel MOSFET device or at least one n-channel MOSFETdevice, wherein drain and gate terminals of said MOSFET device areconnected with said buffer amplifier input, and source and bulkterminals of said MOSFET device are connected with said common node,said second circuit comprises a parallel connection of at least onefifth circuit and at least one sixth circuit, said fifth circuitcomprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein a drain terminal of said MOSFET deviceis connected with said common node, and all other terminals of saidMOSFET device are connected with said reference voltage, and said sixthcircuit comprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein drain and gate terminals of said MOSFETdevice are connected with said common node, and source and bulkterminals of said MOSFET device are connected with said referencevoltage.
 29. A method of constructing a high impedance circuit, saidmethod comprising: forming on an integrated chip at least one p-channeltransistor and at least one n-channel transistor coupled in circuit toprovide high impedance.
 30. The method of claim 29 and wherein said highimpedance comprises a symmetrical high impedance.
 31. The method ofclaim 30 wherein said transistors comprise diode-connected CMOScomponents.
 32. The method of claim 29 wherein said forming at least onetransistor includes forming at least one p-channel MOSFET device or atleast one n-channel MOSFET device, connecting a drain terminal of saidMOSFET device with an input of said buffer amplifier and connecting allother terminals of said MOSFET device with a reference voltage.
 33. Themethod of claim 27 wherein said forming includes forming at least onep-channel MOSFET device or at least one n-channel MOSFET device,connecting drain and gate terminals of said MOSFET device with an inputof said buffer amplifier and connecting source and bulk terminals ofsaid MOSFET device with a reference voltage.
 34. The method of claim 27wherein said forming comprises forming at least one first p-channelMOSFET device and at least one first n-channel MOSFET device, connectinga drain terminal of said first MOSFET device with an input of saidbuffer amplifier and connecting all other terminals of said first MOSFETdevice with a reference voltage, and forming at least one secondp-channel MOSFET device or at least one second n-channel MOSFET device,connecting drain and gate terminals of said second MOSFET device with aninput of said buffer amplifier and connecting source and bulk terminalsof said second MOSFET device with a reference voltage and connectingsaid first and second device in parallel.
 35. The method of claim 27wherein forming said circuit comprises forming the series connection ofat least one first circuit and at least one second circuit, said firstcircuit being connected between said buffer amplifier input and a commonnode between said first circuit and said second circuit, and said secondcircuit being connected between said common node and said referencevoltage, said first circuit comprises a parallel connection of at leastone third circuit and at least one fourth circuit, said third circuitcomprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein a drain terminal of said MOSFET deviceis connected with said buffer amplifier input, and all other terminalsof said MOSFET device are connected with said common node, and saidfourth circuit comprising at least one p-channel MOSFET device or atleast one n-channel MOSFET device, wherein drain and gate terminals ofsaid MOSFET device are connected with said buffer amplifier input, andsource and bulk terminals of said MOSFET device are connected with saidcommon node, said second circuit comprises a parallel connection of atleast one fifth circuit and at least one sixth circuit, said fifthcircuit comprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein a drain terminal of said MOSFET deviceis connected with said common node, and all other terminals of saidMOSFET device are connected with said reference voltage, and said sixthcircuit comprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein drain and gate terminals of said MOSFETdevice are connected with said common node, and source and bulkterminals of said MOSFET device are connected with said referencevoltage.
 36. A microphone, comprising: a transducing assembly forconverting an input sound into an electrical signal; a buffer amplifierfor amplifying said electrical signal; and a high input impedance inputcircuit for said buffer amplifier, said high input impedance circuitcomprising a diode-connected MOSFET circuit.
 37. The circuit of claim 36wherein said MOSFET circuit is integrated on a single integrated circuitchip with said buffer amplifier/preamplifier.
 38. The circuit of claim36 wherein said MOSFET circuit comprises at least one p-channeltransistor coupled in circuit with at least one n-channel transistor.39. The circuit of claim 36 wherein said MOSFET circuit includes saidhigh impedance circuit comprises at least one p-channel MOSFET device orat least one n-channel MOSFET device, and wherein a drain terminal ofsaid MOSFET device is connected with said buffer amplifier input, andall other terminals of said MOSFET device are connected with saidreference voltage.
 40. The circuit of claim 36 wherein said MOSFETcircuit includes said high impedance circuit comprises at least onep-channel MOSFET device or at least one n-channel MOSFET device, andwherein drain and gate terminals of said MOSFET device are connectedwith said buffer amplifier input, and source and bulk terminals of saidMOSFET device are connected with said reference voltage.
 41. The circuitof claim 36 wherein said high impedance circuit comprises a parallelconnection of at least one first circuit and at least one secondcircuit, said first circuit comprising at least one p-channel MOSFETdevice and at least one n-channel MOSFET device, wherein a drainterminal of said MOSFET device is connected with said buffer amplifierinput, and all other terminals of said MOSFET device are connected withsaid reference voltage and said second circuit comprising at least onep-channel MOSFET device or at least one n-channel MO SFET device,wherein drain and gate terminals of said MOSFET device are connectedwith said buffer amplifier input, and source and bulk terminals of saidMOSFET device are connected with said reference voltage.
 42. The circuitof claim 36 wherein said high impedance circuit comprises the seriesconnection of at least one first circuit and at least one secondcircuit, said first circuit being connected between said bufferamplifier input and a common node between said first circuit and saidsecond circuit, and said second circuit being connected between saidcommon node and said reference voltage, wherein said first circuitcomprises a parallel connection of at least one third circuit and atleast one fourth circuit, said third circuit comprising at least onep-channel MOSFET device or at least one n-channel MOSFET device, whereina drain terminal of said MOSFET device is connected with said bufferamplifier input, and all other terminals of said MOSFET device areconnected with said common node, and said fourth circuit comprising atleast one p-channel MOSFET device or at least one n-channel MOSFETdevice, wherein drain and gate terminals of said MOSFET device areconnected with said buffer amplifier input, and source and bulkterminals of said MOSFET device are connected with said common node,said second circuit comprises a parallel connection of at least onefifth circuit and at least one sixth circuit, said fifth circuitcomprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein a drain terminal of said MOSFET deviceis connected with said common node, and all other terminals of saidMOSFET device are connected with said reference voltage, and said sixthcircuit comprising at least one p-channel MOSFET device or at least onen-channel MOSFET device, wherein drain and gate terminals of said MOSFETdevice are connected with said common node, and source and bulkterminals of said MOSFET device are connected with said referencevoltage.